The trend of the system on a chip (SoC) and multi-radio integration urges the need for low cost, low spurious tone, and highly reconfigurable frequency synthesizers. There has been increasing interest in exploring the mostly digital architecture for a phase locked loop (PLL) that replaces the bulky analog circuit components. This type of PLL architecture offers a significant potential for exploring digital signal processing (DSP) algorithms that are not possible in the conventional analog PLL architecture; however, it does incur the overhead of time-to-digital conversion and may introduce quantization noise.
Due to the fully integrated design of SoC implementations, the frequency synthesizer is often physically close to other noise interferers, such as digital circuits, clock buffers and high power analog circuits. These noisy interferences can be coupled into the PLL through various paths, such as the substrate, bonding wires, and power supplies. The noisy interferences often appear as spurious tones (spurs) in the PLL output spectrum. Moreover, the spurious tones can be generated internally by the PLL operation, such as those associated with operation of a fractional-N divider. As a result, the ability to reject spurs associated with internal and external sources becomes an important consideration in the PLL design. Conventionally, spur rejections are implemented via analog approaches, such as separating power supplies, increasing power-supply-rejection-ratio (PSRR), and careful layout. However, performance is still limited by the matching and parasitic coupling paths.